1. Field of the Invention
The invention relates in general to a logic circuit, and more particularly to a technique for improving a semi-dynamic flip-flop.
2. Description of the Related Art
A semi-dynamic flip-flop, an element commonly applied in digital logic circuits, has a dynamic front end and a static rear end. FIG. 1 shows a typical semi-dynamic flip-flop circuit implemented by a complementary metal oxide semiconductor (CMOS). The flip-flop 100 in FIG. 1 includes a discharging circuit 111, a pre-charging circuit 112, an adjusting circuit 113, a first storage circuit 114, an output circuit 115 and a second storage circuit 116. The flip-flop 100 samples an input signal D according to a clock signal CK to produce sampled results as signals Q and QB. Operations of the flip-flop 100 are briefly described below.
When a falling edge of the clock signal CK appears, the flip-flop 100 enters a pre-charging phase. Through a transistor P1 in the pre-charging circuit 112, a power supply end VDD charges a node X to pull the voltage of the node X to a high level. The first storage circuit 114 stores the high level of the node X. Transistors P2 and N5 in the output circuit 115 are turned off, which is in equivalence disconnecting the connection between the intermediate node X and an output node Q, in a way that the second storage circuit 116 continues storing a previous status of the sampled result QB. As the clock signal CK becomes a low level, a delay clock signal CKD in the adjusting circuit 113 also becomes a low level. As such, an output node Y of the adjusting circuit 113 is then in high level that further turns on a transistor N3 in the discharging circuit 111. However, since a transistor N is turned off by the clock signal CK, the level of the node X remains unaffected regardless of the level of the input signal D.
When a rising edge of the clock signal CK appears, the flip-flop 100 enters an evaluation phase (i.e., a phase in which the flip-flop 100 samples the input signal D). At this point, if the input signal D is in low level, the level of the node X remains unaffected and is kept at a high level. If the node Q previously has a low level, no influence is posed on the sampled result QB when the transistor N5 is turned on. In contrast, if the node Q previously has a high level, the turning on of the transistor N5 pulls down the voltage of the node Q to a low level such that the sampled result QB becomes a high level. After a delay period contributed by three logic gates in the adjusting circuit 113 following the appearance of the rising edge of the clock signal CK, the node Y becomes a low level such that the transistor N3 is turned off. By turning on the transistor N3, the input signal D is prevented from changing from a high level to a low level, and the discharging circuit 111 discharges the node X. Such design provides the flip-flop 100 with an edge-triggered characteristic.
When the flip-flop 100 enters the evaluation phase, the discharging circuit 111 discharges the node X to a low level if the input signal D is in high level. The first storage circuit 114 later stores the low level of the node X. The node X with a reduced level turns on a transistor P2 in the output circuit 115, in a way that the node Y has a high level and the sampled result QB is in low level.